1. Field of the Invention
Example embodiments relate to a semiconductor memory device, and more particularly a semiconductor memory device configured to control a power-up signal according to an internal voltage and an active mode.
2. Description of the Related Art
In general, a power-up signal generation circuit in a semiconductor memory device refers to a circuit serving to reset the semiconductor memory device. Typically, a power supply voltage VDD is supplied from outside to operate the semiconductor memory device. The voltage level of the power supply voltage VDD starts from 0V and increases to a target voltage level with a constant slope. When directly receiving such a power supply voltage VDD, all circuits of the semiconductor memory device may malfunction due to the effect of the increasing power supply voltage. Therefore, in order to prevent such a malfunction, the semiconductor memory device includes a power-up signal generation circuit which changes the level of a power-up signal such that the external voltage VDD is supplied to respective circuits after the power-up signal is changed to a stable voltage level. Here, the power-up signal is a signal having a level that increases during a power-up period according to the level of the power supply voltage VDD, and the power-up signal level transits to a logic low level after the power-up period. During the power-up period, the level of the power supply voltage VDD supplied to the semiconductor memory device approaches a preset level (hereafter, referred to as a target level).
FIG. 1 is a circuit diagram illustrating the configuration of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional memory device includes a power-up signal generation circuit 1 and an internal circuit 2. The power-up signal generation circuit 1 is configured to generate a power-up signal PWRUP having a level that increases according to the level of an internal voltage VINT, which increases from 0V with a constant slope like a power supply voltage VDD, and then transits to a logic low level after a power-up period is completed. The internal circuit 2 is configured to receive the internal voltage VINT after the power-up period and buffer an input signal IN to generate an output signal OUT. Furthermore, the internal circuit 2 receives the power-up signal PWRUP and couples the output signal OUT to a ground voltage VSS to perform a reset operation in the power-up period.
Referring to FIG. 2, the operation of the semiconductor memory device configured in such a manner will be described as follows.
FIG. 2 is a diagram illustrating the level of a power-up signal which is generated according to the level of a target voltage in the power-up signal generation circuit of FIG. 1.
Referring to FIG. 2, when the target voltage is set at a high value VTG1 to stably reset the internal circuit 2 of the semiconductor memory device, the level of the internal voltage VINT decreases in cases where the current consumption of the semiconductor memory device increases in a period t3˜t4 after a power-up period t0˜t2. At this time, a period X in which the level of the internal voltage VINT becomes lower than the target voltage VTG1 may occur. In this case, a repower-up occurs to change the power-up signal PWRUP to a logic high level. That is, the output signal OUT of the internal circuit 2 is reset according to the power-up signal PWRUP which is generated at a logic high level in the period X, and causes an operation error of the semiconductor memory device. When the target voltage is set at a low value VTG2 to prevent such a repower-up, the power-up signal PWRUP is generated at a low level in the power-up period t0˜t1. Therefore, since the output signal OUT of the internal circuit 2 is not reset, a reset operation error of the semiconductor memory device may occur.